Radio frequency (RF) transceivers can be found in numerous applications, particularly in the field of wireless communications and radar sensors. In the automotive sector, there is an increasing demand for radar sensors used in so-called “adaptive cruise control” (ACC) or “radar cruise control” systems. Such systems may be used to automatically adjust the speed of an automobile so as to maintain a safe distance from other automobiles ahead.
Modern radar systems make use of highly integrated RF circuits, which may incorporate all core functions of an RF front-end of a radar transceiver in one single package (single chip transceiver). Such RF front-ends usually include, inter alia, a voltage controlled oscillator (VCO), power amplifiers (PA), mixers, and analog-to-digital converters (ADC).
Frequency Modulated Continuous Wave (FMCW) radar systems use radar signals whose frequency is modulated by ramping the signal frequency up and down. Such radar signals are often referred to as “chirp signals” or simply as chirps, wherein frequency is ramped up in an up-chirp and ramped down in a down-chirp. For generating such chirp signals the radar transmitter may include a voltage controlled oscillator (VCO) which is controlled by a digital-analog-converter (DAC). That is, the frequency ramp is generated in the digital domain, the digital values are converted to an analog control signal, which controls the frequency of the VCO. However, such an implementation usually requires a high precision DAC as well as a frequency stabilization (in view of temperature drift and parameter variations due to the manufacturing process). Alternatively, the VCO may be operated in a phase-locked loop (PLL) including a multi-modulus frequency divider. In such an implementation, the frequency is modulated by appropriately tuning the division ratio of the multi-modulus frequency divider. In practice, fractional-N frequency dividers may be used, which allow to digitally set a rational (non-integer) number as division ratio. However, the division ratio should be adjusted in each clock cycle of the PLL. As the PLL usually operates at comparably high frequencies (and therefore the PLL clock cycle is comparably short) a fully digital control of the division ratio is resource-intensive and thus difficult to implement. Therefore, there is a need for an improved frequency ramp-generation in PLL based RF frontends.